Thermal management of electronics can become an issue as the functions, speed, and features thereof increase. These increases typically enhance power requirements of devices, which can be addressed by allocating additional sinking space and/or increasing air flow. However, such solutions may prove to contradict such goals as miniaturization of electronics.
3-D integrated circuits (“3DIC”) were invented to address the scaling challenge by stacking 2-D dies and connecting them in the third-dimension. In a 3DIC package, multiple dies are stacked, for example, on logic die or processor die, to improve performance, bandwidth, and/or functionality. However, since all dies are thermally coupled together, the heat from the last die at the bottom of the stack flows in to the upper die. Thus, when multiple dies are stacked together it becomes challenging to manage thermal energy in the 3DIC package as the primary heat dissipation path is in one direction only.
Although secondary heat dissipation paths exist, they can have relatively large thermal resistance properties that cause the heat flow into the path to dissipate a small percentage of the thermal energy. Unfortunately, the foregoing can either limit the power dissipation in a stack of dies in a 3DIC package or increase the junction temperature limit of dies to increase the power dissipation in the 3DIC package, both of which can impact performance, functionality, or bandwidth in the 3DIC package.